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| geometry process details principal device types cmpt3090l cxt3090l czt3090l cmxt3090l gross die per 4 inch wafer 6,285 process cp309 power transistor npn - low saturation transistor chip process epitaxial planar die size 41.3 x 41.3 mils die thickness 9.0 mils base bonding pad area 9.4 x 9.2 mils emitter bonding pad area 12.8 x 10.2 mils top side metalization al - 30,000? back side metalization ag - 12,000? e b backside collector r1 www.centralsemi.com r4 (22-march 2010)
process cp309 typical electrical characteristics www.centralsemi.com r4 (22-march 2010) |
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